An Efficient Time-Domain Frequency Shifter Hardware Architecture for 4G Systems

Felipe A. P. de Figueiredo, Orlando R. Pereira, Anderson F. Torquato, Fabbryccio A. C. M. Cardoso

Abstract


One of the very first operations carried out by the Physical Random Access Channel (PRACH) receiver at base station side in LTE and LTE-A systems is the extraction of relevant preamble signal through a time-domain frequency shift operation. This operation translates the PRACH signal back to base band which is necessary for preamble detection. This paper presents the hardware architecture and implementation details on Field Programable Gate Array (FPGA) devices of a configurable and optimized time-domain frequency shifter. It is a hardware-efficient and accurate architecture for converting the relevant received PRACH signal into base band before further processing. The
architecture is manly based on a customized Numerically Controlled Oscillator (NCO) for generating complex exponentials using only adders, a Look-Up Table (LUT) and plain logic resources. The main advantage of the proposed arctecture is that it eliminates the need for storing a large number of long
complex exponential sequences by employing a single LUT and exploiting quarter wave symmetry of the basis waveform. Simulation results show that the proposed customized NCO architecture provides high Spurious Free Dynamic Range (SFDR) signals using minimal amount of FPGA resources. The
resulting of spur suppression ranges from approximately 62 to 153 dB without using Taylor Series correction.


Keywords


LTE, PRACH, NCO, time-domain frequency shift, FPGA.

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References


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